The provision of interconnections in the design of a COB (capacitor over bit line) cell of DRAM is particularly important. In the conventional design, a bit line is twisted to allow the capacitor to contact the substrate. FIG. 1 illustrates such a conventional design. An active area 100 is formed over a substrate. A contact hole 110 is subsequently formed over portions of the active area 100. Then, a bit line contact 120 is aligned with and formed over the contact hole 110. Finally, a bit line 130 is formed on the bit line contact 120. Portions of the bit line 130 overlap with the bit line contact 120 to form electrical interconnections and than turn back to an off-axis position of active area as bypassing the node contact plug to leave a enough isolation spacing from the node contact. The path of the bit line 130 is thus twisted as a consequence.
The provision of bit lines that are twisted, rather than substantially straight, results in many disadvantages. Series resistance and parasitic capacitance degrade the bit signal as well as raise the resolution and overlay difficulties in wafer processing steps. One possible solution to this limitation could be to twist the orientation of the active area instead of the bit line. However, such a design induces other processing or material issues that still more involving in device manufacturing.
As the urge for higher packing density of DRAM, the planner dimension (or area) of the unit cell keeps going to smaller and smaller via the advances in the lithographic system and the self aligned contact (SAC) technology. However, because of the tolerance of isolation thickness in SAC etching as well as the polishing level variation in CMP planarization, a definite height in vertical is still in need. The aspect ratio of the cell node contact ( or bit line contact in CUB cell) goes still worse and worse. This makes the reliability of the contact resistance and/or the substrate damage become uncontrollable. A two-step contact structure, which uses projected landing pads or recessed landing plugs raised from substrate as step buffering for the second contact forming steps, has been undertaken commonly by most of the DRAM chip supplier.